Sandy Bridge (microarchitecture)
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This article contains information about scheduled or expected future computer chips. It may contain preliminary or speculative information, and may not reflect the final specification of the product. |
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Sandy Bridge is the code name for a processor that is being developed by Intel and is the planned successor to Nehalem. Intel is already into the development process for Sandy Bridge. Sandy Bridge uses the 32 nm manufacturing methods from Westmere (formerly known as Nehalem-C) and applies it to the new Sandy Bridge microarchitecture[1]. The former codename for this core was Gesher (means 'bridge' in Hebrew), but that codename was abandoned on 17 April 2007 because a political party in Israel is also named Gesher, as mentioned in Justin Rattner's keynote at IDF Spring 2007[2]. Intel's plans are to introduce new microarchitectures every two years, so this processor should debut in 2010. In keeping with its tick-tock principle, the 22 nm shrink of Sandy Bridge is due out in 2011.
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[edit] Architecture
Sandy Bridge's specifications are reported to be as follows, according to a presentation made by Intel in December 2006: [3]
- 4 GHz clock speed.
- 4 to 8 out-of-order cores, possibly up to 32 cores.
- Without SSE: 8 GFLOPS/core, 32-64 GFLOPS/processor.
- With SSE: 28 GFLOPS/core, 112-224 GFLOPS/processor.
- 32 KB L1 cache/core, (3 clocks).
- 512 KB L2 cache/core, (9 clocks).
- 2-3 MB L3 cache/core (33 clocks), most likely pooled and dynamically allocated among the cores.
- 64 bytes cache line width.
- 256 bytes Ring bandwidth.
- 0-512 MB GDDR / fast DRAM.
- 64 GB/s GDDR / fast DRAM memory bandwidth.
- 17 GB/s memory bandwidth per QuickPath link with 50 ns latency.
According to a PC Watch article [1], Sandy Bridge will focus on power efficiency. Performance will be increased without a core size increase. Dynamic Turbo allows the CPU power to exceed the TDP value when the rest of the platform is relatively cool. The frequency gain can be up to 37% for one minute.
Intel has said that Sandy Bridge will have new instructions called Advanced Vector Extensions (AVX).[4] These instructions are an advanced form of SSE. The data path is widened from 128 bits to 256 bits, the two-operand instruction limit is increased to four operands, and advanced data rearrangement functions are included. AVX is suited for floating-point-intensive applications. [2] Features of AVX include mask loads, data permutes, increased register efficiency and use of parallel loads, as well as smaller code size. The improvements of AVX will allow it to deliver up to double the peak FLOPS compared to before.
[edit] References
- ^ Kubicki, Kristopher. Intel Life After "Conroe". DailyTech. Retrieved on 2007-03-03.
- ^ Demerjian, Charlie. Justin Ratner brings out the babes. The Inquirer. Retrieved on 2007-05-20.
- ^ Davis, Ed. Tera Tera Tera Slide #31. Retrieved on 2007-06-01.
- ^ Jason Cross (March 17, 2008). Intel Offers Peek at Nehalem and Larrabee. ExtremeTech.
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[edit] See also
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