Intel 8086
From Wikipedia, the free encyclopedia
 |
This article needs additional citations for verification. Please help improve this article by adding reliable references. Unsourced material may be challenged and removed. (December 2007) |
| Intel 8086 Central processing unit |
|
 |
|
| Produced: | From 1978 to 1990s |
| Manufacturer: | Intel |
| Max CPU clock: | 5 MHz to 10 MHz |
| Instruction set: | x86-16 |
| Package: | 40 pin DIP |
The 8086[1] is a 16-bit microprocessor chip designed by Intel and introduced on the market in 1978, which gave rise to the x86 architecture. Intel 8088, released in 1979, was essentially the same chip, but with an external 8-bit data bus (allowing the use of cheaper and fewer supporting logic chips[2]), and is notable as the processor used in the original IBM PC.
Contents |
[edit] History
[edit] Background
In 1972, Intel launched the 8008, the first 8-bit microprocessor[3]. It implemented an instruction set designed by Datapoint corporation with programmable CRT terminals in mind, that also proved to be fairly general purpose. The device needed several additional ICs to produce a functional computer, in part due to its small 18-pin "memory-package" which prevented a separate address bus (Intel was primarily a DRAM manufacturer at the time).
Two years later, in 1974, Intel launched the 8080[4], employing the new 40-pin DIL packages originally developed for calculator ICs to enable a separate address bus. It had an extended instruction set source (not binary) compatible with the 8008 and also included some 16-bit instructions to make programming easier. The 8080 device, often described as the first truly useful microprocessor, was nonetheless soon replaced by the 8085 which could cope with a single 5V power supply instead of the three voltages of earlier chips.[5] Other well known 8-bit microprocessors that emerged during these years were Motorola 6800 (1974), Microchip PIC16X (1975), MOS Technology 6502 (1975), Zilog Z80 (1976), and Motorola 6809 (1977), as well as others.
[edit] The first x86 design
The 8086 was originally intended as a temporary substitute for the ambitious iAPX 432 project in an attempt to draw attention from the less-delayed 16 and 32-bit processors of other manufacturers (such as Motorola, Zilog, and National Semiconductor) and at the same time to top the successful Z80 (designed by former Intel employees). Both the architecture and the physical chip were therefore developed quickly (in a little more than two years[6]), using the same basic microarchitecture elements and physical implementation techniques as employed for the one year earlier 8085, which it would also function as a continuation of. Although not directly source compatible, it was designed so that assembly language for the 8085, 8080, or 8008 could be automatically converted into equivalent (sub-optimal) 8086 source code, usually with little or no hand-editing, i.e. the programming model and instruction set was (loosely) based on the 8085. However, the 8086 design was expanded to support full 16-bit processing instead of the fairly basic 16-bit capabilities of the 8080/8085.
8086 was implemented[7] using a mix of random logic and microcode and was designed using depletion load nMOS circuitry using around 20,000 active transistors (29,000 counting all ROM and PLAs sites). It was soon moved to Intels new refined nMOS manufacturing process called HMOS (later to HMOS-II and III) originally developed for manufacturing of fast static RAMs.[8] The chip measured 33mm² and minimum feature size was 3.2μm.
While less known than the 8088 chip, the legacy of the 8086 is enduring; references to it can still be found on most modern computers in the form of the Vendor entry for all Intel device IDs which is "8086". It also lent its last two digits to Intel's later extended versions of the design, such as the 286 and the 386, all of which eventually became known as the x86 family.
[edit] Details
[edit] Buses and operation
All internal registers as well as internal and external data buses are 16 bits wide, firmly establishing the "16-bit microprocessor" identity of the 8086. A 20-bit external address bus gives a 1 MB (segmented) physical address space (220 = 1,048,576). 16-bit I/O addresses give 64 KB of separate I/O space. (216 = 65,536). The control pins carry the essential signals for all external operations.
The data bus was multiplexed with the address bus, this was only slightly diminishing performance however, as other factors, more important for this particular chip, shadow this design choice; transfers of 16 (or 8) bit quantities are done in a four-clock memory access cycle. 8086 instructions varied from 1 to 6 bytes. Therefore, fetch and execution were concurrent (as it remains in today's x86 designs): The bus interface unit feeds the instruction stream to the execution unit through a 6 byte prefetch queue (a form of loosely coupled pipelining), speeding up operations on register and immediates, while memory operations unfortunately became slower (4 years later, this performance problem was fixed with the 80186 and 80286). The performance gain over the 8080 and 8085 resulting from the full (instead of partial) 16-bit architecture, the operand versus operation orthogonalizations, and other enhancements, were still fairly significant, despite cases where the older chips may be faster (see below).
The maximum linear address space is limited to 64 KB, simply because internal registers are only 16 bits wide. Programming over 64 KB boundaries involves adjusting segment registers (see below) and is therefore fairly awkward (and remains so until the 80386). Some control pins have more than one function depending upon whether the device is operated in the "min" or "max" mode. The former is intended for small single processor systems whilst the latter is for medium or large systems using more than one processor. The processor had some new instructions (not present in the 8085) to better support stack based high level programming languages such as Pascal and C; some of the more useful ones were push immed, push mem-op, and ret size (several others would be added in the subsequent 80186, 80286, and 80386 designs).
[edit] Registers and instructions
The 8086 has eight (more or less general) 16-bit registers including the stack pointer, but excluding the instruction pointer, flag register and segment registers. Four of them could also be accessed as eight 8-bit registers (see picture).
Due to a compact encoding inspired by 8085 and other 8-bit processors, most instructions were one-address or two-address operations which means that the result were stored in one of the operands. At most one of the operands could be in memory, but this memory operand could also be the destination, while the other operand, the source, could be either register or immediate. A single memory location could also often be used as both source and destination which, among other factors, further contributed to a rather small executable code footprint, comparable to most eight bit machines.
Although the degree of orthogonality between registers and operations were greater than in 8085, it was still low, and registers were also sometimes used implicitly by instructions. While perfectly sensible for the assembly programmer, this complicated register allocation for compilers compared to more regular contemporary 16- and 32-bit processors (such as VAX or 68000); on the other hand, compared to contemporary 8-bit processors (such as 8085 or 6502), it was significantly easier to generate code for the 8086 design.
As mentioned above 8086 also featured 64 KB of 8-bit (or alternatively 32 K-word or 16-bit) I/O space. A 64 KB (one segment) stack growing towards lower addresses is supported by hardware; 2-byte words are pushed to the stack and the stack top (bottom) is pointed out by SS:SP. There are 256 interrupts, which can be invoked by both hardware and software. The interrupts can cascade, using the stack to store the return address.
[edit] Segmentation
There were also four segment registers that could be set from index registers. The segment registers allowed the CPU to access one mebibyte + 64 KiB - 16 bytes of memory in an odd way. Rather than just supplying missing bytes, as in most segmented processors, the 8086 shifted the segment register left 4 bits and added it to the offset address, thus:
- physical address = segment×16 + offset
The physical memory address was therefore 20 bits wide (while both segment and offset were 16 bits). As a result of this scheme, segments overlapped, making it possible to have up to 4096 different pointers addressing the same location. While acceptable, and even useful, for assembly language programming (where control of the segments was complete) it caused confusion and was considered poor design by most people, forcing entirely new concepts (near and far keywords) into languages such as Pascal and C; data and/or code could be managed within near 16-bit segments, or a large data structure (or many and/or large procedures) could be accessed by far pointers (32-bit segment:offset pairs) reaching the full physical address space.
Although this scheme made expanding the address space to more than 220 bytes more difficult, it was nevertheless soon expanded by a new MMU-controlled addressing scheme in the 80286's protected mode. Later, and on top of this, 80386 expanded the whole general purpose registers set (and hence, the offsets) to 32 bits, thereby enabling a linear addressing range of 232 bytes (with a total range of 236). However, those chips were, for a long period of time, often used in real mode, remaining compatible with older OSes.
In a similar way, early programs could ignore the segments, and just use plain 16-bit addressing, which allowed 8-bit software to be easily ported to the 8086. The authors of MS-DOS took advantage of this by providing an Application Programming Interface very similar to CP/M. This was important when the 8086 was new, because it allowed many existing CP/M applications to be quickly made available on the new platform, which greatly eased the transition.
[edit] Performance
Execution times for typical instructions (in clock cycles):
Timings are best case, depending on prefetch status, instruction alignment, and other factors.
MOV reg,reg: 2, reg,im: 4, reg,mem: 8+EA, mem,reg: 9+EA, mem,im: 10+EA cycles ALU reg,reg: 3, reg,im: 4, reg,mem: 9+EA, mem,reg: 16+EA, mem,im: 17+EA cycles
JMP reg: 11, JMP label: 15, Jcc label: 16 (cc = condition code)
MUL reg: 70..118 cycles IDIV reg: 101..165 cycles
EA: time to compute effective address, ranging from 5 to 12 cycles.
As can be seen from these tables, operations on registers and immediates were fast (between 2 and 4 cycles), while memory-operand instructions and jumps were quite slow; jumps took more cycles than on the simple 8080 and 8085, and the 8088 (used in the IBM PC) was additionally hampered by its narrower bus. The reasons why most memory related instructions were so slow were threefold:
- The execution and fetch units were loosely coupled; this is efficient for instruction prefetch, but less optimal for jumps and random data access.
- Address generation calculations were largely performed by microcode routines.
- The address and data buses were multiplexed in order to fit a standard 40-pin dual in-line package.
It should be noted, however, that the memory access performance was drastically enhanced with Intel's next generation chips; the 80186 and 80286 both had address calculation in hardware, saving many cycles; 80286 also had separate (non-multiplexed) address and data buses.
[edit] Floating point
The 8086/8088 could be connected to a mathematical coprocessor to add floating point capability. The Intel 8087 was the standard math coprocessor, operating on 80-bit numbers, but manufacturers like Weitek soon offered higher performance alternatives.
[edit] Chip versions
The clock frequency was originally limited to 5 MHz (IBM PC used 4.77 MHz, 4/3 the standard NTSC color burst frequency), but the last versions in HMOS were specified for 10 MHz. HMOS-III and CMOS versions were manufactured for a long time (at least a while into the 1990s) for embedded systems, although its successor, the 80186/80188, has been more popular for embedded use.
[edit] Derivatives and clones
Compatible and, in many cases, enhanced versions were manufactured by Fujitsu, Harris/Intersil, OKI, Siemens AG, Texas Instruments, NEC, and AMD. For example, the NEC V20 and NEC V30 pair were hardware compatible with the 8088 and 8086, respectively, but incorporated the instruction set of the 80186 along with some (but not all) of the 80186 speed enhancements, providing an drop-in capability to upgrade both instruction set and processing speed without manufacturers having to modify their designs. Such relatively simple and low power 8086-compatible processors in CMOS are still used in embedded systems.
The electronics industry of the Soviet Union was able to replicate the 8086 through both industrial espionage and reverse engineering. The resulting chip, K1810BM86, was pin-compatible with the original Intel 8086 and had the same instruction set. This IC was the core of Soviet-made PC-compatible ES1840 and ES1841 desktops. However, in hardware these computers had significant differences from their authentic prototypes (respectively PC and PC/XT): the K1810BM86 was a copy from Intel 8086, not Intel 8088, and the data/address bus circuitry was designed independently of original Intel products.
[edit] Notable bugs
8086/8088 CPUs produced prior to 1982 had a severe interrupt bug. IBM provided an upgrade free of charge to affected PCs. Processors remaining with original 1979 markings are quite rare; they have become collectors' items.
[edit] Microcomputers using the 8086
- One of the most influential microcomputers of all, the IBM PC, used the Intel 8088, a version of the 8086 with an eight-bit data bus (as mentioned above).
- The first commercial microcomputer built on the basis of the 8086 was the Mycron 2000.
- The IBM Displaywriter[citation needed] word processing machine and the Wang Professional Computer, manufactured by Wang Laboratories, also used the 8086. Also, this chip could be found in the AT&T 6300 PC (built by Olivetti).
- The first Compaq Deskpro used an 8086 running at 7.14 MHz, but was capable of running add-in cards designed for the 4.77 MHz IBM PC XT.
- The FLT86 is a well established training system for the 8086 CPU still being manufactured by Flite Electronics International Limited in Southampton, England
- The IBM PS/2 models 25 and 30 were built with an 8MHz 8086
[edit] Notes and references
- ^ Microprocessor Hall of Fame. Intel. Retrieved on 2007-08-11.
- ^ It also permitted cheap 8080-family chips to be used (such as the 8254 CTC, 8255 PIO, and 8259 PIC which were used in the IBM PC design). In addition, it made PCB layout simpler and boards cheaper, as well as demanding fewer (1 or 4-bit wide) DRAM chips.
- ^ using enhancement load pMOS logic
- ^ using enhancement load nMOS logic
- ^ made possible with depletion load nMOS logic (the 8085 was later made using HMOS processing, just like the 8086)
- ^ Two years from idea to product was considered fast for a complex design (almost no CAD-tools were used)
- ^ 8086 used less microcode than many competitors designs, such as the MC68000 and others
- ^ Fast static RAMs (as fast as bipolar) in MOS technology was an important product for Intel during this period.
[edit] See also
[edit] External links
|
|||||||||||||||||
