Talk:Propagation delay

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[edit] Removed section about metastability

The following section was removed:

Often one logic gate is connected to another that is connected back to the first. When an invalid input is applied to such a system, the amount of time from when the external inputs to the system become stable and valid to the time the output of both logic gates become stable and valid can be far longer than the normal propagation delay. This is the problem of metastability in electronics.

Looping back gates generates latches and is strongly discouraged, but possible. Invalid input relates to observance of setup and hold timing requirements of a synchronous flip-flop. Failure to observe these requirements does precipitates metastability, which has nothing to do with simple, unclocked logic. Michagal 16:52, 15 March 2007 (UTC)

[edit] Typical propagation delay?

I think this article should give some idea as to what the typical propagation delay for a logic gate is. At least the approx order of magnitude - i.e. is it a few ns / ms etc? And does it vary much between different types of logic gates? --Vclaw 23:53, 12 October 2007 (UTC)