Gekko (microprocessor)
From Wikipedia, the free encyclopedia
| Power Architecture |
|---|
| Historical |
|
POWER • PPC6xx • PowerPC-AS • POWER2 • POWER3 • G4 • POWER4 • Gekko • AIM alliance |
| Current |
|
PowerPC • e200 • e300 • e500 • e600 • PA6T • POWER5 • POWER6 • PPC4xx • PPC750 • PPC970 • CBEA • Xenon • Broadway |
| Future |
| Related Links |
|
RISC • System p • System i • Power.org • PAPR • PReP • CHRP • more... |
Gekko is a 32-bit PowerPC microprocessor custom made by IBM in 2000 for Nintendo to use as the CPU in their sixth generation game console, the Nintendo GameCube.
Contents |
[edit] Development
Gekko's role in the game system was to facilitate game scripting, artificial intelligence, physics and collision detection, custom graphics lighting effects and geometry such as smooth transformations, and moving graphics data through the system.
The project was announced in 1999 when IBM and Nintendo agreed to a one billon dollar contract for a CPU running at approximately 400 MHz. IBM chose to modify their existing PowerPC 750CXe processor to suit Nintendo's needs, such as tight and balanced operation alongside the "Flipper" graphics processor. The customization was to the bus architecture, DMA, compression and floating point unit which support a special set of SIMD instructions. The CPU made ground work for custom lighting and geometry effects and could burst compressed data directly to the GPU.
IBM's customization led to performance that exceeded Nintendo's specifications. The Gekko is considered to be the direct ancestor to the Broadway processor, also designed and manufactured by IBM, that powers the Wii console.
[edit] Features
- PowerPC G3 based 3-way superscalar RISC core
- 485 MHz
- 32-bit Integer unit
- 64-bit double precision FPU, usable as 2×32-bit SIMD for 1.9 Gflops performance
- Roughly 50 new SIMD instructions, geared towards 3D graphics
- 64-bit enhanced 60x bus to GPU/chipset at 162 MHz clock with 1.3 GB/s peak bandwidth
- 64 kB 8-way associative L1 cache (32/32 kB instruction/data). 256 KB on-die, 2-way associative L2 cache
- 1125 DMIPS (dhrystone 2.1)
- 180 nm IBM six layer, copper-wire process. 43 mm² die
- 1.8 V for logic and I/O. 4.9 W dissipation
- 27×27 mm PBGA package with 256 pins
