Visual Instruction Set
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Visual Instruction Set, or VIS, is a SIMD instruction set for SPARC CPUs, implemented on all UltraSPARC and some SPARC64 processors.
There are three versions of VIS. VIS 1.0 and VIS 2.0 are included in existing SPARC processor designs; VIS 3.0 is planned for implementation on the upcoming Rock processor.[1]
VIS re-uses existing SPARC 64-bit floating point registers to hold multiple 8, 16, or 32-bit integer values. In this respect VIS is more similar to the design of MMX than other SIMD architectures such as SSE/SSE2/AltiVec. However, Intel's MMX has only 8 registers shared with the FPU stack, while SPARC processors usually have a much larger number of registers (one characteristic of RISC architecture).
As with the SIMD instruction set extensions on RISC processors, VIS strictly conform to the main principle of RISC: keep the instruction set concise and efficient. This design is very different from comparable extensions on CISC processors, such as MMX/SSE/SSE2/SSE3/SSE4/3DNow!. Basically, this RISC principle can make the pipelines more simple and efficient and consequently bring better throughput and performance.
However, Intel/AMD can easily add new instruction set extensions to x86/x64 processors while Sun must be very careful in adding new extensions to SPARC processors, which may be considered an advantage of CISC over RISC. Sometimes programmers must use several VIS instructions to accomplish an operation that can be done with only one MMX/SSE instruction, but it should be kept in mind that fewer instructions doesn't automatically result in better performance.
VIS includes a number of operations primarily for graphics support, so most of them are for only for integer. These include 3D to 2D conversion, edge processing and pixel distance.
There are three ways to use VIS in code:
- Use inline assembly
- Use inline template in VSDK, similar to compiler intrinsics, which have C function like interfaces
- Use the mediaLib multimedia library, which has C function interfaces. It uses VIS on SPARC platforms (and MMX/SSE/SSE2 on x86/x64 platforms) to accelerate multimedia application execution
[edit] References
- ^ Liang He; Harlan McGhan (May 2005). MT mediaLib for Chip MultiThreaded (CMT) Processors. Sun Microsystems, Inc.. Retrieved on 2007-12-03.

