Image:Switch box.svg
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Switch_box.svg (SVG file, nominally 443 × 289 pixels, file size: 13 KB)
| This is a file from the Wikimedia Commons. The description on its description page there is shown below.
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| Description |
Whenever a vertical and a horizontal channel intersect there is a switch box. In this architecture, when a wire enters a switch box, there are three programmable switches that allow it to connect to three other wires in adjacent channel segments. (In terms of the usual FPGA terminology then, Fs = 3.) The pattern, or topology, of switches used in this architecture is the planar or domain-based switch box topology. In this switch box topology, a wire in track number one connects only to wires in track number one in adjacent channel segments, wires in track number 2 connect only to other wires in track number 2 and so on. The figure below illustrates the connections in a switch box. |
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| Source | |
| Date |
2007-04-29 |
| Author |
Traced by User:Stannered from an work by en:User:Ignaciomella |
| Permission (Reusing this image) |
GFDL |
| Other versions | en:Image:Switch box.gif |
File history
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| Date/Time | Dimensions | User | Comment | |
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| current | 16:31, 29 April 2007 | 443×289 (13 KB) | Stannered | ({{Information |Description=Whenever a vertical and a horizontal channel intersect there is a switch box. In this architecture, when a wire enters a switch box, there are three programmable switches that allow it to connect to three other wires in adjacent) |
