SerDes
From Wikipedia, the free encyclopedia
A Serializer/Deserializer (SerDes pronounced sir-dees) is a pair of functional blocks commonly used in high speed communications. These blocks convert data between serial data and parallel interfaces in each direction. Although the term "SerDes" is generic, in speech it is sometimes used as a more pronounceable synonym for SGMII.
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[edit] Generic function
The generic SerDes function is decomposed into two functions. The first is the Parallel-to-Serial converter, sometimes called the Parallel In Serial Out (PISO) block. The second is the Serial to Parallel converter, sometimes called the Serial In Parallel Out (SIPO) block.
The PISO block canonically has a parallel clock in and a collection of data lines coming into it. It may have some sort of Phase-locked loop in it to multiply the incoming parallel clock up to the serial frequency. This may also be located outside of the block. The simplest form of the PISO has a single shift register that receives the parallel data once per parallel clock and shifts it out at the higher serial clock rate. Implementations may also have a double-buffered register.
The SIPO block canonically has serial clock and data inputs. The serial clock may have been recovered from the data stream using a clock recovery technique. The SIPO block then divides the incoming clock down to the parallel rate. Implementations typically have a double-buffer of registers. One register is used to clock in the serial stream, and the other is used to hold the data for the slower, parallel side.
Implementations of SerDes are sometimes combined with implementations of encoding/decoding blocks in single blocks. The purpose of encoding/decoding is typically to place at least statistical bounds on the rate of signal transitions to allow for easier clock recovery in the receiver, to provide framing, and to provide DC balance.
[edit] 8B/10B encoding
A common coding scheme used with SerDes is 8B/10B encoding. This supports DC-balance, provides framing, and guarantees transitions. The guaranteed transitions allow a receiver to extract the embedded clock. The control codes allow framing, typically on the start of a packet. The typical 8B/10B SerDes parallel side interfaces have 1 clock line, 1 control line and 8 data lines.
Such serializer plus 8B/10B encoder and deserializer plus decoder blocks are defined in the Gigabit Ethernet specification.
[edit] 64B/66B encoding
Another common coding scheme used with SerDes is 64B/66B encoding. This scheme statistically delivers DC-balance and transitions through the use of a scrambler. Framing is delivered through the deterministic transitions of the added framing bits.
Such serializer plus 64B/66B encoder and deserializer plus decoder blocks are defined in the 10 Gigabit Ethernet specification. The transmit side is composed of the collection of a 64B/66B encoder, a scrambler, and a gearbox that converts the 66B signal to a 16 bit interface. A further serializer then converts this 16 bit interface into a fully serial signal.
[edit] Parameters of SerDes
Parameters of SerDes include:
- Inputs and Outputs
- Rates of the interfaces
- Density and integration level
- Built-in self-test functionality
- Built-in system-test functionality
- Clock generation functionality
- Clock-data or data recovery functionality
- Jitter transfer of clock functions
- Transmit and receive equialization capabilities
- Signal integrity
- Protocol specific functionality
- Framing functionality
- Encoder/decoder functionality
- Power dissipation
- Voltage levels and tolerance
- Temperature range
- Reliability
[edit] See also
- A list of common protocols that use 8B/10B encoded SERDES is found on the 8B/10B page.
