OpenRISC 1200

From Wikipedia, the free encyclopedia

Block diagram of the OR1200 processor architecture
Block diagram of the OR1200 processor architecture[1]

The OpenRISC 1200 (OR1200) is a synthesizable CPU core maintained by developers at OpenCores.org. The OR1200 design is an open source implementation of the OpenRISC 1000 RISC architecture.

Contents

[edit] Architecture

The IP core of the OR1200 is implemented in the Verilog HDL. As an open source core, the design is fully public and may be downloaded and modified by any individual. The official implementation is maintained by developers at OpenCores.org. The implementation specifies a power management unit, debug unit, tick timer, programmable interrupt controller, central processing unit (CPU), and memory management hardware[2]. Peripheral systems and a memory subsystem may be added using the processor's implementation of a standardized 32-bit WISHBONE bus interface[3]. The OR1200 is intended to have a performance comparable to an ARM10 processor architecture[4].

Block diagram of the OR1200 CPU/DSP
Block diagram of the OR1200 CPU/DSP[5]

[edit] CPU/DSP

The OR1200 CPU is an implementation of the 32-bit ORBIS32 instruction set architecture (ISA)[6]. The ISA has five instruction formats and supports two addressing modes: register indirect with displacement, and PC-relative[7]. The implementation has a single-issue 5-stage pipeline and is capable of single cycle execution on most instructions[8]. The CPU also contains a [Multiply-accumulate|MAC]] unit in order to better support digital signal processing (DSP) applications [9].

[edit] Memory Management

The OR1200 design uses a Harvard memory architecture and therefore has separate memory management units (MMUs) for data and instruction memories. These MMUs each consist of a hash-based 1-way direct-mapped translation lookaside buffer (TLB) with page size of 8 KB[10] and a default size of 64 entries. The TLBs are individually scalable from 16 to 256 entries[11]. There is also an one-way direct-mapped cache each for both the instruction memory and for the data memory. Each cache has a default size of 8 KB[12], but both are individually scalable between 1 and 64 KB[13]. The MMU includes support for virtual memory[14].

[edit] Performance

Under the worst case, the clock cycle for the OR1200 is 250 MHz at a 0.18 µm 6LM fabrication process. Using the Dhrystone benchmark, a 250 MHz OR1200 processor performs 250 Dhrystone millions of instructions per second (DMIPS) in the worst case. Estimated power usage of a 250 MHz processor at a .18µm process is less than 1W at full throttle and less than 5mW at half throttle.

[edit] Applications

Generally, the OR1200 is intended to be used in a variety of embedded applications, including but not limited to internet and telecom, portable device, home entertainment, and automotive applications[15]. Some open source software, such as Linux and μClinux, has been ported over to the OR1200 platform[16]. The GNU toolchain (including GCC) has also been successfully ported to the architecture to aid in software development[17]. The OR1200 has been successfully tested in an MP3 player application[18].

[edit] Implementations

The OR1200 has been successfully implemented using FPGA and ASIC technologies[19].

[edit] History

The OR1200 was preceded by and was based upon the OpenRISC 1000 (OR1k) core (for which the architecture was named).[20] The OR1200 was an advancement upon this earlier design, which had been seen production by Beyond Semiconductor, though this company has now created its own proprietary OR1k-based design[21].

[edit] Notes

  1. ^ Core Specification p. 9
  2. ^ Core Overview
  3. ^ Core Specification, p. 25
  4. ^ Core Specification, p. 8
  5. ^ Core Specification p. 10
  6. ^ Core Overview
  7. ^ Architecture Manual, p. 16
  8. ^ Core Overview
  9. ^ Core Specification, p.12
  10. ^ OpenRISC 1200
  11. ^ Core Overview
  12. ^ OpenRISC 1200
  13. ^ Core Overview
  14. ^ OpenRISC 1200
  15. ^ Core Overview
  16. ^ Core Overview
  17. ^ OpenRISC Resources
  18. ^ OpenRISC 1200
  19. ^ OpenRISC 1200
  20. ^ OpenRISC 1200
  21. ^ Beyond Semiconductor

[edit] References

[edit] External Links