Image:NOR gate layout.png
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NOR_gate_layout.png (600 × 433 pixels, file size: 22 KB, MIME type: image/png)
[edit] Summary
Shows a CMOS implementation of a NOR gate. Also used at http://www.sccs.swarthmore.edu/users/06/adem/engin/e77vlsi/lab3/
[edit] Licensing
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I, the copyright holder of this work, hereby release it into the public domain. This applies worldwide. In case this is not legally possible, |
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| Date/Time | Dimensions | User | Comment | |
|---|---|---|---|---|
| current | 15:30, 23 November 2007 | 600×433 (22 KB) | Ademkader (Talk | contribs) | (This is an image I made using L-edit. It shows the physical layout of a NOR gate.) |
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