Talk:Minimig

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Feature? Surely that must read 'future'? 213.10.120.175 08:54, 2 August 2007 (UTC)

[edit] Edits

  • Amiga is re-implemented using an FPGA, not as a FPGA.
  • The linked Amiga Custom Chipset article nonexistant.
  • Source code were relased not specifications. But schematics,gerber etc.. were included.
  • PIC is a specific microcontroller, and a link to the generic term 'microcontroller' is good to hint on AVR. Not imply PIC is the only microcontroller available.
  • The hidden comment "This is NOT the TNT23 project" is only for those more deeply involved. Just confuses other persons. —Preceding unsigned comment added by Electron9 (talk • contribs) 13:51, August 28, 2007 (UTC)

[edit] Various claims..

  • The clock_dcm.v takes 4.433619 MHz from the PAL colour crystal and outputs 4.433619*(32/5) = 28.3751616 MHz to feed Agnus etc.. Any other frequences is an even division from there. Because only DCMs in the Xilinx FPGA may create fractional parts of another frequency.
  • The Freescale M68000 CPU most certainly don't run at 16 MHz. Because it get it's clock from the fpga (Pin101 CPU_CLK). Which produce this frequency with the clock_dcm() function. Thus 4.433619*(32/5)/4 = 7.0937904 MHz. Which is the standard frequency for an OCS A500 Amiga.
  • The synchronous bus may run at 4.433619*(32/5)/2 = 14.1875808 MHz, but I'm not sure. However there's not reason for it to run at anything but a even multiple below or equal to 28.3751616 MHz or thereof.
  • The MCU (PIC18) 20.000 MHz clock crystall is not involved with the FPGA or m68k-cpu, see connection diagram.
  • Minimig specification improvements might be better written as deltas. Ie what changed from version X to Y.
  • Please do check electrical diagrams and verilog sources before modifying anything related to this again.
  • Power intake is +5V DC, and current usage is approximately ~100 mA according to Dennis. (with basic setup)

Electron9 (talk) 10:58, 12 February 2008 (UTC)