MaverickCrunch

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The MaverickCrunch is a floating point math coprocessor core by Cirrus Logic, currently implemented in silicon alongside an ARM920T main core in their 200MHz EP9302 EP9307 EP9312 and EP9315 System-on-Chip integrated circuits.

It has its own instruction set which implements 32- and 64-bit integer and IEEE-754 floating point addition, subtraction, multiplication, negation, absolute value and comparison, a set of multiply-and-accumulate functions, conversion between integer and floating point values and instructions to move data between itself and the ARM registers or memory. It has 16 64-bit registers, four 72-bit multiply-and-accumulate registers and a status register.

It operates in parallel with the main processor, both processors receiving their instructions from a single 32-bit instruction stream. Thus, to use it efficiently, integer and floating point instructions must be interleaved so as to keep both processors busy.

Three versions of the silicon for this unit have been issued: "D0" and "D1"/"E0"/"E1" and "E2" (the silicon revision number is the 5th and 6th characters of the second row of text on the chip housing). All have many subtle instruction timing bugs, which either give junk results or clobber registers when certain instruction sequences occur separated by a certain distance in time. The GNU Compiler Collection contains a code generator for the FPU and has flags that try to work around the defects, though these have never worked. Among the attempts to fix them are:

These seem to work but neither passes the stringent "paranoia" floating point verification suite.

For this reason, some systems derived from this chip do not support MaverickCrunch; see the links below. However, an article in the Gentoo wiki claims to have achieved a working set of patches.

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