Talk:Instructions per second

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[edit] Critics on MIPS

The article has a lengthy description of the acronyms critics of MIPs use, but does not state why they are critical of the metric. I suggest explaining why they are, for those people who read the article and have not taken computer architecture.

—Preceding unsigned comment added by 65.6.47.129 (talk) 19:25, 2 September 2007 (UTC)

Those critics are personal opinions that are not appropriate for Wikipedia. I think the critics are mainly caused by ignorance of what MIPS means. Quite many people seem to mix MIPS with MNOPS (Million NOP instructions per second). That is, they assume that you can take the fastest possible execution time of the fastest instruction (such as NOP), calculate how many such instructions could be executed in second, and then call that MIPS. That would, of course, not be an useful method for comparing processor speeds. But that is not MIPS. MIPS is the average execution time of insturctions in real world applications.
-- PauliKL (talk) 13:34, 14 March 2008 (UTC)

The acronym MIPS is inherently wrong due to the fact the unit of measure of time "second" has to be specified accordingly to the international standards spec. as a lowercase "s".

Following the correct example in the first sentence by the user "65.6.47.129" above, MIPs is the formally correct horthografy.

-- AT 213.156.52.121 (talk) 19:20, 27 April 2008 (UTC)
No. The correct acronym is MIPS, since that is the acronym that has been commonly aggreed. If international standard specs (SI) was to be used, the acronym would be MI/s. But that is not the point. The main thing is what MIPS actually means and what does it measure. --PauliKL (talk) 18:54, 15 May 2008 (UTC)

[edit] Changes

Removed Pentium 4 data for error. Pentium 4s typically have MIPS between 3,000 and 20,000, depending on year of release.

Also removed data based on erroneous formula.

Added Year 2004 data for budget 32 bit and 64 bit PCs.

[edit] Several instructions per clock cycle

  • Is that right about 20,000 MIPS for the Pentium and 10,000 for the Celeron? Can they really do several instructions per clock tick? Bubba73 19:15, 12 Jun 2005 (UTC)
  • Theoretically yes. Starting from the 486 which is a 386CPU and 387FPU on the same die, most processors can theoretically do more than 1 instruction per cycle. Note that cycle does not equal clock.
That is not true. 486 can definitely not execute more than 1 instruction per clock cycle. And many instructions take more than 1 clock cycle, so the average is significantly less than 1 instruction/cycle. Adding FPU on same die does not change that. It is insignificant whether the FPU is on the same die or on different die. It does not change the way the processor works, and it does not have effect on the MIPS value. Since the days of the first FPU's, everybody has known the fact that adding FPU does not change MIPS value. MIPS is about integer performance of the CPU itself. It does not take account floating point calculations. And adding external units such as graphics processors does not have effect on MIPS value either. - PauliKL (talk) 21:27, 24 February 2008 (UTC)
P.S. Added the missing headings on talk page - PauliKL (talk) 22:22, 24 February 2008 (UTC)
  • Ever since the first Pentium processor they have been superscalar, which means they can perform more than one instruction per clock. Now for some modern MIPS calculations: the K7 and K8 (Athlon and Althon 64 from AMD) have 3 integer units each and can issue 3 insructions per clock, and can complete most non-memory integer operations in a single clock. The fastest single-core Athlon 64 is 2.8GHz, which gives a theoretical limit of 2.8e9 * 3 / 1e6 = 8400 MIPS. The Intel Pentium 4 has 2 simple integer units and one complex unit. It can perform a select subset of simple integer operations (add,subtract, and shifts on the Prescott) at a rate of 4 instructions per clock, or a single less simple operation. The fastest single-core Pentium 4 is 3.8GHz, which gives a peak of 15200 MIPS if you are doing the 4 instructions per clock, or down to 3800 MIPS for less-simple instructions. None of this includes things you can do with the SIMD instructions. Given the ambiguity in the Pentium calculations I'll just start by adding the Athlon 64 to give an idea of current speed of modern processors.
  • According to SySoft SANDRA Dhrystone ALU benchmark, an Athlon FX-57 clocked at 2.8GHz yield 12000 MIPS, an Athlon 64 X2 3800+ with two cores at 2GHz yield 17200 MIPS, using the same benchmark, I reached 25150 MIPS by overclocking my Athlon 64 X2 3800+ to 2.8GHz. I took the liberty to edit the Athlon 64 MIPS accordingly, if you don't beleive me, 'bench 'em yourself.
  • MIPS is now largely replaced by MTOPS which manufacturers are required to disclose by law. (United States Department of Commerce Export Administration Regulations 15 CFR 774 (Advisory Note 4 for Category 4). )
  • Links to MTOP calculations : [[1]]

[[2]]

[edit] Timeline

  • Aren't timelines usually in chronological order? Shogun 01:07, 21 March 2006 (UTC)
yep, they are. I corrected the table. jidan 15:56, 15 May 2006 (UTC)

[edit] New proposed timeline

Hi, instead modifying the table inside the article, I write here the new proposed timeline based on http://www.frc.ri.cmu.edu/users/hpm/book97/ch3/processor.list.txt. However the last entries with the processor name only (from Intel pentium pro) should be removed/changed, because I think that is more realistic to calculate the IPS for the enteire system (CPU/bus/memory) and not only the processor. I also found very useful the cost of the system compared to the value of USD in the 1997, to understand the customer target. The sources are various (specint, speedmark, winsscore..) compared to the MIPS. May be not perfect, but I think it is a good point to start. Please to leave some comment. --Trek00 02:54, 5 February 2007 (UTC)

Processor IPS Year Cost (USD 1997)
Pencil and Paper 0.0119 IPS 1892
ENIAC 2.89 kIPS 1946 600'000
UNIVAC I 5.75 kIPS 1951 930'000
Whirlwind 69.4 kIPS 1955 200'000
Atlas 1.4 MIPS 1961 5'000'000
CDC 6600 8.76 MIPS 1964 5'000'000
CDC 7600 25.7 MIPS 1969 10'000'000
IBM System/370-195 17.3 MIPS 1972 8'000'000
Altair 8800 (Intel 8080 at 2 MHz) 10 kIPS 1974 500
Cray 1 150 MIPS 1976 10'000'000
VAX 11/780 1 MIPS 1977 200'000
Apple II 20 kIPS 1977 1'300
Commodore 64 200 kIPS 1982 500
Macintosh 128K (Motorola 68000 at 8 MHz) 520 kIPS 1984 2'500
Cray 2 824 MIPS 1985 10'000'000
Macintosh II (Motorola 68020) 2.5 MIPS 1987 3'000
PC Brand 386/25 (Intel 386DX at 25 MHz) 4.3 MIPS 1988 2'450
Amiga 3000 (Motorola 68030) 12.5 MIPS 1990 3'300
Gateway 486DX2/66 (Intel 486DX at 66 MHz) 30.9 MIPS 1991 3'900
Power Macintosh 7100/66 (PowerPC 601 at 66 MHz) 100 MIPS 1994 2'899
ARM 7500FE 35.9 MIPS at 40 MHz 1996
Gateway G6-200 (Intel Pentium Pro at 200 MHz) 350 MIPS 1997 2'949
Power Macintosh G3 (PowerPC G3 at 266 MHz) 500 MIPS 1997 2'000
Zilog eZ80 80 MIPS at 50 MHz 1999
Intel Pentium III at 500 MHz 820 MIPS 1999 2'500
Power Macintosh G4 (PowerPC G4 at 450 MHz) 856 MIPS 1999 2'500
ASCI White 10000000 MIPS 2000 110'000'000
AMD Athlon 3561 MIPS at 1.2 GHz 2000
AMD Athlon XP 2400+ 5935 MIPS at 2.0 GHz 2002
Pentium 4 Extreme Edition 9726 MIPS at 3.2 GHz 2003
System X 20000000 MIPS 2004 6'000'000
ARM Cortex A8 2000 MIPS at 1.0 GHz 2005
Xbox360 IBM "Xenon" Triple Core 6400 MIPS at 3.2 GHz 2005
IBM Cell All SPEs 12096 MIPS at 3.2 GHz 2006
AMD Athlon FX-57 12000 MIPS at 2.8 GHz 2005
AMD Athlon 64 3800+ X2 (Dual Core) 14564 MIPS at 2.0 GHz 2005
AMD Athlon FX-60 (Dual Core) 18938 MIPS at 2.6 GHz 2006
Intel Core 2 X6800 27079 MIPS at 2.93 GHz 2006
IBM Cell BE (All the SPEs) 25600 MIPS (FLOPS) at 3.2 GHz 2006
Intel Core 2 Extreme QX6700 57063 MIPS at 3.33 GHz 2006

[edit] Cell Data is blatantly incorrect

Guys -- The data you posted about the Cell processor is just plain incorrect. Please update the page. For the record:

Cell runs at 3.2 GHz. Cell has one dual-threaded fully 64-bit Power Architecture core. This core, not including its AltiVec vector processor, does 6400 MIPS... although these are 64-bit instructions so the comparison to 32-bit processors is really not too valid. (Should we claim that it's 12800 "32-bit MIP equivalents"?) In ADDITION to the above, the Cell has 8 single-threaded 128-bit processor cores. That adds 25600 MIPS or 102400 32-bit MIP equivalents... for a total of 38400 (115200).

FLOPS have nothing to do with the above. In FLOPS, the Cell does over 200 single-precision GFLOPS and in the high teens in double precision. As of today (30 Mar 2007), information on the next-generation processor has been released... although I am not at liberty to disclose its performance until someone cites it.

The figure you cited was not a peak value (as cited for other processors). Instead, you took the performance on a given benchmark (Linpack) in FLOPS... which are not comparable to MIPS.

The Cell Team at IBM

No, you can not multiply the MIPS value by 2 using the excuse that processor has some 64 bit instructions. One 64 bit instruction is still just one instruction. And, let's face it, 64 bit instructions are rarely used in real world applications. After all, 64 bit data is quite rare. Most common data is 8 bit (character data, 8 bit/channel RGB data etc.). In addition, most applications use only 32 bit instruction set in order to be compatible with older processors, so 64 bit processor is no faster than 32 bit one. But even if the program is compiled to use 64 bit insturctions, it will only be around 2% to 5% faster than the 32 bit version.
Indeed, FLOPS measurement should not be mixed with MIPS. MIPS is only about integer performance. No matter how powerful FPU is included with the CPU, it does not have effect on the MIPS value of the CPU.
There is no such thing as "peak value" in MIPS measurement. MIPS is the average number of instructions executed by the processor when running a real world application. (Well, the term "peak MIPS" is sometimes used to say that it is the speed of the CPU when the application fully fits in L1 cache so that the memory access is not slowing down the operation. Which is the case with Dhrystone benchmark, for example.)
-- PauliKL (talk) 22:09, 24 February 2008 (UTC)

[edit] Given MIPS ratings not correct

The MIPS ratings given in the table seem to be incorrect. For example, 8080 at 2 MHz has been given value 640 kIPS (0.64 MIPS), which is impossible. The fastest instructions on 8080 take 4 clock cycles. Thus, 2 MHz 8080 can execute maximum of 0.5 million instructions per second.

However, max number of instructions per second is not MIPS. MIPS is calculated from weighted average of instruction execution times.

I recall Intel has given 8080 rating of 0.08 MIPS, which sounds more correct, considering the fact that a 8 bit processor needs multiple instructions to perform a single 32 bit operation.

Another example: Zilog eZ80 has been given rating of 80 MIPS at 50 MHz. As far as I know, eZ80 is not a superscalar processor, so it can not execute more than 1 instruction / clock cycle. Since it is a 8 bit processor, the MIPS rating must be significantly less than 50 MIPS.

PauliKL (talk) 18:08, 23 January 2008 (UTC)

[edit] MIPS = MHz?

If a microprocessor can execute a singular instruction million times per second (MHz), then why can't it execute a million unique instructions within the same timeframe (MIPS)? What is the game-changing constraint here? This article does not explain this rather bizarre behaviour.Anwar (talk) 10:44, 15 May 2008 (UTC)

Huh? What do you mean? MHz is unit of frequency, not unit of instructions per second. In context of processors, MHz is usually used to measure the clock frequency. Traditional CISC processor may require multiple clock cycles to execute one instruction, so they deliver less than 1 MIPS/MHz. RISC processors typically execute every instruction in one clock cycle. In that case, they would execute about as many instructions per second as the MHz value would indicate. Number of instructions executed per second is not same as MIPS, but with 32-bit processors, it is quite close. However, there are processors that can execute multiple instructions in parallel (superscalar). Further, there are processors with multiple cores. These deliver more than 1 MIPS/MHz. --PauliKL (talk) 19:10, 15 May 2008 (UTC)

[edit] IBM 704 & IBM 7030

Could someone add the Mips of the IBM 704 (1954) and the IBM 7030 (1961) to this table? I'm too dumb to do so. tnx in advance. See also new proposed timeline above. Aleichem (talk) 20:37, 8 June 2008 (UTC)