Talk:HyperTransport
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The HyperTransport website claims up to about 12 GB/s transfers, does that mean that it has been expanded to 64-bit (32-bit each way)? —Mulad 20:32 9 Jun 2003 (UTC)
[edit] HT as an FSB replacement
Does HT qualify as an FSB replacement? My understanding (and that of the FSB article) is that an FSB is the connection between the CPU and the MCH, which is not what HT serves as - it serves as an external connector for the CPU to a device of any desired functionality with an HT link (could be a Northbridge/MCP, could be another K8, could be a co-processor as per cHT links...). I want to strike "HT as an FSB replacement" and replace with "HT as an FSB augmentation." HT does not carry data to memory, which is the defining charachteristic of that particular bus (otherwise it becomes "just another interconnect out of the CPU" so to speak).
- Actually I wouldn't say that carrying data to memory is the defining feature of a FSB, instead I would say that a FSB is the main connection from a CPU to the rest of the world. The FSB article itself says as much when it lists the RAM as just one of the things that are connected to over a FSB. I would rather see this subtlety added to the paragraph. Perhaps something like: Many of the processors which utilize HyperTransport including the Opteron and the BCM1480 have an integrated memory controller. In these uses, HyperTransport does not serve as the local connection to memory as in the classical definition of a FSB. However, the HyperTransport does serve as the connection to the memory directly connected to other Opterons (or BCM1480's) when these devices are used in NUMA applications. Brholden 05:33, 16 August 2006 (UTC)
[edit] HT is not a bus
"An electrical bus (sometimes spelled buss) is a physical electrical interface where many devices share the same electric connection. This allows signals to be transferred between devices (allowing information or power to be shared). A bus often takes the form of an array of wires that terminate at a connector which allows a device to be plugged onto the bus." from Wikipedia article bus.
HT is a point-to-point serial interconnect, not a bus. A bus is inherrently parallel, (if my understanding is correct) and shared (HT is not shared...it is point to point). With consensus (or after three days) I will change all references to "HT bus" in this article to "HT Interconnect."
- The HT site itself calls it a bus...[1] Can more than one HT link be called a bus? -Ravedave 22:14, 19 July 2006 (UTC)
- HyperTransport lives in the gray area between serial and parallel interconnects. It uses a mixture of the techniques of both. It is fine to remove some of the uses of "bus", but the one to not remove is as its use as a Front side bus of microprocessors. HyperTransport use as the front side bus of the Opteron/Athlon/Turion microprocessors is the most important application of HyperTransport. The term Front side bus has the broader meaning as the main interface coming out of a microprocessor, independent of its specific implementation. If the word "bus" was removed from this spot, the article would lose meaning. Less important, but along the same lines, the term Computer bus has the additional meaning of a memory-mapped interface independent of the specifics of the interface. (forgot to sign this a while back Brholden 05:33, 16 August 2006 (UTC))
- The article Front side bus concedes that HT is not an FSB "Not technically a front side bus." I understood that FSB was the connection between the CPU and MCH, and there was a lot of dicsussion during the unveiling of the K8 marchitechture that indicated the "FSB" (as it were) would be on-die. The FSB article links to a back side bus article, which makes reference to connections between the CPU and cache, but given that storage is hierachachal, I don't believe this is accurate (in a theoretical sense, not necessarily an electrical one). However, I think that because electrical engineering terminology reflects a very definitive and static reality, it's important that we (as an excyclopedia) are absolutely clear on these topics. Gray area is very bad.
- Yes, and no. An alternate definition of 'bus' is often a set of signals that go from one IC to another. So it may be one "data line" (well, in HT that line is two physical differential traces but I digress) along with its control signals, and we could call it a bus. It gets into grey areas when you start bonding serial channels together into a "bus" but you have no exact data phase alignment between the channels. Is that a bus? I'd say yes - it has many of the similar restrictions as a traditional bus, but some are more relaxed. I just tweaked the article a touch, avoiding the word bus. — RevRagnarok Talk Contrib 03:28, 16 August 2006 (UTC)
- The article Front side bus concedes that HT is not an FSB "Not technically a front side bus." I understood that FSB was the connection between the CPU and MCH, and there was a lot of dicsussion during the unveiling of the K8 marchitechture that indicated the "FSB" (as it were) would be on-die. The FSB article links to a back side bus article, which makes reference to connections between the CPU and cache, but given that storage is hierachachal, I don't believe this is accurate (in a theoretical sense, not necessarily an electrical one). However, I think that because electrical engineering terminology reflects a very definitive and static reality, it's important that we (as an excyclopedia) are absolutely clear on these topics. Gray area is very bad.
- HyperTransport lives in the gray area between serial and parallel interconnects. It uses a mixture of the techniques of both. It is fine to remove some of the uses of "bus", but the one to not remove is as its use as a Front side bus of microprocessors. HyperTransport use as the front side bus of the Opteron/Athlon/Turion microprocessors is the most important application of HyperTransport. The term Front side bus has the broader meaning as the main interface coming out of a microprocessor, independent of its specific implementation. If the word "bus" was removed from this spot, the article would lose meaning. Less important, but along the same lines, the term Computer bus has the additional meaning of a memory-mapped interface independent of the specifics of the interface. (forgot to sign this a while back Brholden 05:33, 16 August 2006 (UTC))
[edit] HT/HTT
Just for Info : HT is the Trademark for Hyper Transport HTT or HT-Tech or HT-Technology is the Trademark for Hyper Threading Technology Denniss 10:23, 14 Dec 2004 (UTC)
[edit] Link width correction
Yes, the maximum supported link width is 32-bit in each direction.
I did some slight changes to the article.
--Eltiel 03:45, 6 September 2005 (UTC)
[edit] Added "Overview" header
This is a nice article about a nice technology. But (couldn't you tell that there was a "but" coming?) the first section is rather long, putting the contents box well down the page. So I added an "Overview" header after the first paragraph. I hope that this makes the article even better. Chris Chittleborough 07:03, 10 November 2005 (UTC)
[edit] HyperTransport an SGI technology?
Several articles I have read claim that hypertransport was originally an sgi technology. Is there any basis to this? I will not add to this article but I think that if proven to be correct, sgi should be given credit in the article. --67.138.72.190 21:53, 29 December 2005 (UTC)
- It was based on the Digital Equipment Corporation's EV7 bus architecture. [2] —Preceding unsigned comment added by 87.246.78.22 (talk • contribs)
[edit] Versions
I know that there are 3 versions (1, 2, and amazingly 3) of Hyper transport, they should probably be in the article. -Ravedave 04:35, 17 May 2006 (UTC)
This seems to have been corrected (see beginning of Overview) Ppchailley 10:45, 30 June 2006 (UTC)
[edit] Intel HyperTransport
I thought that Intel is already using HyperTransport via certain nVidia chipsets?
http://www.guru3d.com/article/mainboard/419/10/
Check out the following pages. —The preceding unsigned comment was added by Ofunniku (talk • contribs) 13:29, 9 March 2007 (UTC).
- A number of non-Intel chipsets use HyperTransport between the devices of the chipset. Some of these chipsets can be used with Intel processors. Brholden 18:47, 9 March 2007 (UTC)
- I'm sorry. I forgot to sign my previous post. I'm kinda new to the discussion pages on wikipedia :) So, will this information be written to the main article? I think it's pretty important. -Ofunniku 5:11, 29 March 2007 (UTC)
Intel does use hypertransport but not as a replacement for the front side bus. It is used occasionally for linking dual and multicore processors together.
- Do you have any sources for this claim ? --Denniss 02:31, 19 June 2007 (UTC)
-
- That is highly unlikely. The only instace that HyperTransport ever appeared on Intel platforms is on nVidia chipsets, as the recent nForce chipsets are designed with HyperTransport in mind. Their Intel-compatible chipsets retain most of the features found on the AMD side. Ofunniku 13:06, 27 July 2007 (UTC)
[edit] Server makers
I'm not sure listing server makers in this article makes much sense. I'm pretty sure if you're building a server that uses AMD Opteron processors, you have to use Hypertransport, and this article is probably not the best place to try to maintain a complete listing of everyone who makes servers that take Opteron processors. For that matter, I think this article would need to list everyone who makes a motherboard that takes Athlon64 and Athlon64 X2 and Athlon64 X4 processors, too (Asus, Tyan, and HP come to mind as examples who make motherboards / desktop PCs that I've personally worked with that I'm pretty sure have Hypertransport.)
So I think it would be better to just make it clear that using those processors effectively requires Hypertransport, and the articles about those processors can contain lists of manufacturers if there's a need to make such a list. JNW2 03:00, 31 October 2007 (UTC)
[edit] re list
agreed that this is not the place for a comprehensive list of HT server manufacturers, but feel that including a few examples for the sake of illustration is OK as long as it's acompanied by a link to a more compehensive list elsewhere. —Preceding unsigned comment added by 68.80.214.27 (talk) 13:11, 28 November 2007 (UTC)
[edit] where's the switch
the article seems to indicate that HT works like a packet switched network but it's not clear how or where the switching takes place. explanaiton welcome. —Preceding unsigned comment added by 68.80.214.27 (talk) 13:13, 28 November 2007 (UTC)
of course if no switch is required an explanation of why not would be fitting.
put differently, if HT works like a network an explanation of the network topology would be helpful. —Preceding unsigned comment added by 68.80.214.27 (talk) 15:01, 28 November 2007 (UTC)
[edit] comparison to other interconnects?
might be interesting to add some comparisons to other high performance cpu/memory interconnect architectures (ie, the DEC interconnect mentioned above, SGI's ccNUMA system, sun's fireplane, HP superdome, the crossbar switches that have appeared in some RISC workstations, etc). —Preceding unsigned comment added by 68.80.214.27 (talk) 13:21, 28 November 2007 (UTC)
[edit] Fair use rationale for Image:HyperTransport logo resized.jpg
Image:HyperTransport logo resized.jpg is being used on this article. I notice the image page specifies that the image is being used under fair use but there is no explanation or rationale as to why its use in this Wikipedia article constitutes fair use. In addition to the boilerplate fair use template, you must also write out on the image description page a specific explanation or rationale for why using this image in each article is consistent with fair use.
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BetacommandBot (talk) 23:10, 22 December 2007 (UTC)
[edit] HyperTransport being compared to PCI?
Is there any reason that the article compares the clockspeeds of HyperTransport to PCI? Even if that was a fair comparison, why not compare it to a more contemporary connection such as PCI-E? —Preceding unsigned comment added by 68.150.216.73 (talk) 05:29, 2 June 2008 (UTC)
