Delay calculation

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Delay calculation is the term used in integrated circuit design for the calculation of the gate delay of a single logic gate and the wires attached to it. By contrast, static timing analysis computes the delays of entire paths, using delay calculation to determine the delay of each gate and wire.

There are many methods used for delay calculation for the gate itself. The choice depends primarily on the speed and accuracy required:

  • Circuit simulators such as SPICE may be used. This is the most accurate, but slowest, method.
  • Two dimensional tables are commonly used in applications such as logic synthesis, placement and routing. These tables take an output load and input slope, and generate a circuit delay and output slope.
  • A very simple model called the K-factor model is sometimes used. This approximates the delay as a constant plus k times the load capacitance.
  • A more complex model called Delay Calculation Language,[1] or DCL, calls a user-defined program whenever a delay value is required. This allows arbitrarily complex models to be represented, but raises significant software engineering issues.
  • Logical effort provides a simple delay calculation that accounts for gate sizing and is analytically tractable.

Similarly there are many ways to calculate the delay of a wire. The delay of a wire will normally be different to each destination. In order of increasing accuracy (and decreasing speed), the most common methods are:

  • Lumped C. The entire wire capacitance is applied to the gate output, and the delay through the wire itself is ignored.
  • Elmore delay[2] is a simple approximation, often used where speed of calculation is important but the delay through the wire itself cannot be ignored. It uses the R and C values of the wire segments in a simple calculation. The delay of each wire segment is the R of that segment times the downstream C. Then all delays are summed from the root.
  • Padé approximations, also call moment matching, are more complex methods analytic methods. The oldest of such methods was AWE,[3] with PRIMA[4] and PVL as more recent and sophisticated variants. These methods are faster than circuit simulation and more accurate than Elmore.
  • DCL, as defined above, can be used for interconnect as well as gate delay.
  • Circuit simulators such as SPICE may be used. This is the most accurate, but slowest, method.

Often, it makes sense to combine the calculation of a gate and all the wire connected to its output. This combination is often called the stage delay.

The delay of a wire or gate may also depend on the behaviour of the nearby components. This is one of the main effects that is analyzed during signal integrity checks.

Contents

[edit] Delay Calculation in digital design

In the context of semi-custom digital design, pre-characterized digital information is often abstracted in the form of the above mentioned 2-D look up table (LUT). The idea behind semi-custom design method is to use block of pre-built and tested components to build something larger, say, a chip.

In this context, the blocks are logic gates such as NAND, OR, AND, etc. Although in reality these gates will be composed of transistors, a semi-custom engineer will only be aware of the delay information from input pin to output pin, called a timing arc. The 2D table represents information about the variablility of the gate's delay with respect to the two independent variables, usually the rate of change of the signal at the input and the load at the output pin. These two variable are called slew and load in design parlance.

A static timing analysis engine will first calculate the delay of the individual cells and string them together to do further analysis.

[edit] Statistical delay calculation

See also: Statistical static timing analysis

As chip dimensions get smaller, the delays of both gates and wires may need to be treated as statistical estimates instead of deterministic quantities. For gates, this requires extensions to the library formats. For wires, this requires methods that can calculate the means and distributions of wire delays. In both cases it is critical to capture the dependence on the underlying variables such a threshold voltage and metal thickness, since these result in correlations among the delays of nearby components. See [5] for an early example.

[edit] References

  1. ^ IEEE standard including DCL
  2. ^ *W. C. Elmore, The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers , Journal of Applied Physics, January 1948, Volume 19, Issue 1, pp. 55-63.
  3. ^ *Pillage, L.T.; Rohrer, R.A., Asymptotic waveform evaluation for timing analysis , IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 9, Issue 4, April 1990, pp. 352 - 366.
  4. ^ *Odabasioglu, A.; Celik, M.; Pileggi, L.T., PRIMA: passive reduced-order interconnect macromodeling algorithm , IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 17, Issue 8, Aug. 1998, pp. 645 - 654
  5. ^ Ying Liu; Pileggi, L.T.; Strojwas, A.J., (1999) Model order-reduction of RC(L) interconnect including variational analysis , proceedings of the 36th Design Automation Conference, 21-25 June 1999, pp. 201 - 206

[edit] See also

[edit] Further reading/External links

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