Talk:Cray-1

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The problem citing the 800 MFLOPS number for the X-MP (the Cray-1's lineage successor) is that this performance figure does NOT correspond to 1982 performance for a 2 processor (then available) X-MP; it more closely corresponds to 4 processor X-MPs on a "good" day which was not until a couple of years later. The text has an impediance mismatch between machine performance and chronology.

--enm 26 Apr 2006 18:00 GMT

Another topic which needs real elaboration is the history of the first planned operating system for the Cray-1 at LANL. This was supposed to be Deimos. An academic paper was written about Deimos, but apparently the message-passing and its Unix-like favor for years put the fear of God in anything smelling like UNIX at LASL (later LANL) and LLL (later LLNL). Why this was and what happened is a lesson for technologists.

--enm 26 April 2006 18:30 GMT

The problem I see with this artical is that thier seems to be inconsistences in the speeds given for the cray-1 and apparently also thiers an accidental use of the acronym MIPS rather then MFLOPS (or megaflops). This article states that In 1975 Cray clammed that the speed was 80 MFLOPS and then give an un-named sorce credit for placed the speed of the Cray-1 at "138–250 MFLOPS". I visited Cray inc's web site and Cray inc claims today that the Cray-1's speed was 160 megaflops (not MIPS). http://www.cray.com/about_cray/history.html

Now I have nrver read of seen any banchmarks for the Cray-1 giving speeds in MIPS and Cray inc. claims it's speed was 160 megaflops, and this artical says 160 MIPS so I think maybe the acronym MIPS was used by accident and ether MFLOPS or megaflops should of bin used instead. Using MIPS may confuse people in to thinking that MIPS and MFLOPS (or megaflops) mean the samething.

But the article is quite clear on the difference: the theoretical performance was 2 instructions at 80 MHz which is 160 million instructions, or MIPS. Floating point operations were not one-cycle, nor could they be dispatched on any cycle, so the FP performance was slower, the 136 MFLOPs number. I don't know where the 80 MFLOPs number came from, it's wrong and I'm removing it. Maury 21:39, 28 November 2006 (UTC)

Contents

[edit] comparison to 2006 ipod shuffle

Gjvo: That's really interesting. Can you provide more details? Mmernex 17:38, 22 May 2007 (UTC)

[edit] Comparison with modern pc prosessors

http://www.tomshardware.com/2007/07/16/cpu_charts_2007/page36.html i think the second table shows relevant Mflops?--Teveten 07:07, 3 October 2007 (UTC)

[edit] History

The first sentence of the history states:

In the early 1974 Cray was working at Control Data on a new machine known as the CDC 8600, the logical successor to his earlier CDC 6600 and CDC 7600 designs.

I think that in [1974]] Cray was working at Cray Research and not at Control Data. Later the history states:

In 1972 the 8600 had reached a dead end.

and a little bit later (without stating a date):

Cray left.

The article about the CDC 8600 states that:

In 1972 Cray decided that he couldn't work under such conditions, and left CDC to form Cray Research.

The article about Cray Research states that:

Cray Research, Inc. (CRI), was founded in 1972 by computer designer Seymour Cray.

So I guess the history should begin with:

In the years 1968 to 1972 Cray was working at Control Data on a new machine known as the CDC 8600, the logical successor to his earlier CDC 6600 and CDC 7600 designs.

since the article about CDC 8600 states that:

Development started in 1968

Therefore I will do the change. Glass Tomato 08:47, 2 November 2007 (UTC)

[edit] Background notes (STAR)

From the article,

... something that might have been obvious had the designers considered Amdahl's Law.

Implying that the designers simply failed to take into account Amdahl's law is a vast over-simplification of the underlying causes of disappointing real-world performance. Amdahl's law is a simple back-of-the-envelope calculation that any idiot can do. I think the STAR's problem may have been an inaccurate estimate of typical workloads. It is all to easy to come up with corner cases that would show a huge speedup with vector processing that are not likely to be found in the real world. For good examples of such toy problems, refer to just about every microbenchmark ever written.

And it's probably likely that any advertised speedups came from inflated or misinterpreted claims spewed by the marketing department of the company, not directly from the designers themselves.

In any case, the claim that the designers were able to engineer a complex piece of technology without understanding one of the simplest principles of parallel programming is laughable. —Preceding unsigned comment added by 24.136.36.147 (talk) 11:43, 9 January 2008 (UTC)

[edit] Addressing

I have my doubts about this sentence: "Addressing was 24-bit, for a maximum of 1 megaword (8 MB) of main memory."

According to my references, data addressing was 22-bit and operated at the word level, allowing a maximum of 4 Mwords (64-bit words). Instruction addressing was also 22-bit, but operated at the instruction parcel level (16-bit parcels). Early models could have a maximum of 1 Mword, but this was later raised to four. Am I wrong? Philip Trueman (talk) 13:30, 3 April 2008 (UTC)

I think you're basically right. There some info in the Cray-1 hardware reference manual [1] which describes the original 1 MW max setup. The memory reference instructions have a 22 bit address field of which the top two bits are said to be unused (that's presumably the original 1 MW physical memory limit). Branches take a 25 bit address (top 3 bits unused); the bottom 2 bits are the parcel address. Finally, the exchange package specifies 22 bit base and limit addresses. So I'd say 4 MW is the max, both for data and for instructions. Paul Koning (talk) 20:23, 3 April 2008 (UTC)

The address registers were 24 bits wide. However, since each of the 4 instruction parcels in a word were addressable (e.g., via a branch instruction), this gave 22 bits of word address for 4 mwords. The early Cray-1 machines were limited by the memory technology of the day - only 1k bits/chip! The Cray-1S used denser technology (4k bits/chip), so could be configured with 4 mwords in the same 12-column footprint of a 1 mword Cray-1. --Wws (talk) 21:45, 4 April 2008 (UTC)