Talk:CPU design

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[edit] Article needs diagrams

  • I think it is essential for this article to display some diagrams that condense and clarify the explanations. I think it's a daunting task to try to understand processor architecture concepts and examples without diagrams. Technical users will have no trouble understanding this immense desolate text, but 'casual' readers and researchers (most people I guess) will likely be disheartened and confused. Can someone with some knowledge in the subject upload/make some simple diagrams? --Cbohorquezm 21:00, 8 May 2006 (UTC)
  • this article could use some pics/diagrams. --ZeWrestler Talk 04:38, 3 October 2005 (UTC)

[edit] Old discussion

Okay, a pretty big edit. Divided the article into sections. Added a bunch of stuff, cleared up the difference between pipelining and superscalar. I think an improved opening paragraph (betwee "general cpu design" and "1960") would be helpful... might do it later. The stuff at the end (under "additional considerations"), some of it I don't think is appropriate for discussions on CPU design (such as the laser-diode bus replacement...). Also, I don't know much about embedded processor design, so I just left that in its own section at the bottom.

Would it be a good idea to have sample designs under each part? Like "486" as an example of a pipelined processor, "Pentium Pro" as an example scalar processor, and Pentium(II? III? I forget) as an example super-scalar processor?

Also, would it be more appropriate to divide this into multiple articles... like an article on instruction pipelining, and take out most of the discussion on that, and a seperate one for superscalar desgin, and for VLIW, etc. etc. There's already a lot of overlap between this and the CISC and RISC articles.

—This unsigned comment is by Mudlock (talk • contribs) 18:02, 15 April 2002.

What is a "one-off design"? This does not seem to be in English. David 20:21 Nov 13, 2002 (UTC)

If no one replies, I'll delete it. David 22:36 Nov 19, 2002 (UTC)

The topic of this article is CPU design. Several paragraphs at the end of the article are not relevant to CPU design but to Computer Architecture, a different topic. I suggest they be deleted. Namely the paragraphs talking about real-time schedulers, and virtual memory. Aug 17, 2004.

Deleted ? No, I *moved* them to computer architecture. --DavidCary 22:51, 17 Aug 2004 (UTC)

the article refers to "solid-state RAM"... is there any other (relevent) kind? i guess you can make mechanical logic, and thus, mechanical SRAM, but i don't think thats what the author has in mind.


As a matter of fact- CRTs were used as RAM. Up until that point, acoustic delay lines were used for computer memory. It was awfully slow to wait for the right bits to come around. Core memory was the first solid-state RAM, embraced because it worked so much better than CRT-based RAM.

I removed some text that seemed inaccurate to me. The author had 32-bit ARMs universally replacing 8-bit processors. Engineers use what's cheapest, and 8-bit CPUs and cores are often smaller and cheaper. Embedded defibrillators, one of the lowest-powered devices on the planet (16 nanoamperes draw), generally use a CMOS CISC core of the 68HC11. The last time I checked, the world's best-selling CPU was an 8-bit CISC microcontroller, the Motoroloa 6809. Also, the 6502 is an 8-bit RISC machine, not a CISC. The 6502 even uses combinatorial decoding of instructions, with no microcode. The Acorn RISC Machine (ARM) was designed as a 32-bit 6502.

I think it's debatable whether the 6502 is RISC or CISC. The 6502 has variable-length instructions (RISC almost all have fixed-length instructions), and a few instructions that do 2 zero-page memory reads and a general memory write (RISC almost all have at most a single memory reference per instruction). --DavidCary 22:51, 17 Aug 2004 (UTC)

It would be really cool to have a historical table of the world's best-selling CPU (and its volume) year-by-year. --DavidCary 22:51, 17 Aug 2004 (UTC)

[edit] data processing capabilities and bcd

The article says that "the S/360 [had] the first instruction set designed for data processing, rather than mathematical calculation. I do not believe that this is accurate, given the instruction of the UNIVAC I, the IBM 1401 and others, where mathematical calculations were definitely NOT the only objective.

Additionally, the article states that "the S/360 system was the first computer to make major use of binary coded decimal". Again, to contradict this, the 1401, a predecessor of the S/360 used BCD for its numerical format, as did the IBM 1620.

[edit] No mention of out-of-order execution

This article is missing the major computer architecture topic of the 90's - out-of-order execution. It jumps from superscalar to speculative execution & VLIW (neither technique fully successful in the market) while out-of-order chips are selling in the 100's of millions each year (complete success). It was the complexity of OOO execution which started VLIW to be re-examined by research. Dyl 06:34, Aug 12, 2004 (UTC)


[edit] a large bed

The article currently says

IBM does have a large bed, VERY large. Of course, on the other hand, IBM may sort of NEED to get all of these customers on-board if they want to stay on top of the CPU development game.

Huh ? What do you mean by "bed" ? --DavidCary 22:51, 17 Aug 2004 (UTC)

Those few paragraphs talking about IBM are:

  • not NPOV
  • talk about the economics of processor manufacture, not CPU design directly (or even computer architecture)

So in my opinion, are not appropriate for this article. Dyl 22:47, Sep 22, 2004 (UTC)

[edit] feature proximity

i was going to make a stub for Feature proximity but figured it might be better to just put a sentence about it in an existing article? research.sun.com

thoughts? - Brewthatistrue 23:53, 24 Jun 2005 (UTC)

Sounds blue sky, but that doesn't stop mention in articles. It doesn't belong in the CPU design article, though. Maybe in the Packaging section of Integrated circuit. -R. S. Shaw 02:33, 25 Jun 2005 (UTC)

[edit] more futuristic ideas

"Baby Steps to our Future: Future Microprocessors" by Ron Fenley http://www.hal-pc.org/journal/03feb/column/baby/baby.html

[edit] split this page?

I'm thinking about splitting this page into multiple articles:

  1. History of General Purpose CPUs
  2. CPU Design (current sections on actually how to build a CPU)
  3. CPU Architectural concepts
  4. Embedded CPUs

The title "design" doesn't match most of the contents, which is computer architecture/microarchitecture. Comments? Dyl 07:27, 1 February 2006 (UTC)

  • This article could definitely use refocusing. Regarding the mentioned subject areas:
    1. History of General Purpose CPUs
      This is already very well covered by History of computing hardware and Central processing unit, both of which are substantial articles which have reached Featured Article status. The only history this article might need is that of design tecniques, not the CPU products.
    2. CPU Design (current sections on actually how to build a CPU)
      Yes, this should be the content of this article.
    3. CPU Architectural concepts
      These matters should be in a separate article. There already exists an article Computer architecture, which is in great need of additional and better material. Applicable text in this article should be removed and merged into Computer architecture (or conceivably other articles in Category:Computer architecture). There is also a Microarchitecture article that deals with the physical CPU architecture.
    4. Embedded CPUs
      This likely could go into the design section of Embedded system. There is also Microcontroller.
    -R. S. Shaw 04:27, 2 February 2006 (UTC)
Too small, splitup not justified. Said: Rursus ☻ 08:19, 9 June 2008 (UTC)

[edit] myth of smaller sets of instructions

This article (currently) perpetuates the myth that the "reduced" in RISC means that there are fewer instructions in the instruction set.

I'm pretty sure that the people designing RISC processors didn't really care too much about how many instructions were in the instruction set.

Instead, designers tried to simplify, or "reduce", individual instructions so that individual instructions could be executed very fast. "Fast" in 2 ways:

  • try to get things "done" as quickly as possible after one clock tick -- so that they could reduce the time from one clock tick to the next. Since the clock speed of a CPU is limited by the *slowest* instruction, even if the program currently running on it never uses that instruction, simplifying that one instruction (perhaps by breaking it into 2 or 3 new instructions, expanding the instruction set) allows one to speed up the clock speed, speeding up all the other instructions.
  • try to change the hardware so instructions executed in fewer clock ticks (preferably in a single cycle). Having a fixed limit of "all instructions execute in 1 cycle" also simplifies pipelining and eliminates microcode, indirectly leading to faster clock speed.

Since this seems to be a common myth, should we discuss the myth in the article? (I see it is already discussed in Reduced instruction set computer). --70.189.77.59 13:15, 15 October 2006 (UTC)

[edit] High-end processor economics

Under this heading:

4 Markets 4.1 General Purpose Computing 4.1.1 High-end processor economics

I'm not sure if Fujitsu is making it's own high-end processors. If it is a source needs to be added. Thanks. Scifiintel 18:55, 25 February 2007 (UTC)

In the article, I just added the external link for it . Dyl 13:19, 26 February 2007 (UTC)

[edit] clockless CPUs

The sequential logic article currently links to [[CPU_design#clockless_CPUs]], a section of this article that apparently no longer exists. To which article has that information moved? Or was it accidentally deleted and needs to be restored? --75.37.227.177 04:53, 26 July 2007 (UTC)

As far as I can tell, that section was accidentally deleted in this summary-less edit: http://en.wikipedia.org/w/index.php?title=CPU_design&diff=prev&oldid=109091120 . So I am restoring that accidental deletion. If it was really *moved* to some other article, not deleted, please tell me to where it moved. --68.0.124.33 (talk) 02:28, 13 February 2008 (UTC)

I see now there are 2 copies of that "clockless CPU" section. One here in "CPU design". The other in History of general purpose CPUs. What should we do about it? --68.0.124.33 (talk) 04:08, 13 February 2008 (UTC)

The deletion in Feb '07 was not accidental. You can see that user:Dyl added it to History of general purpose CPUs in this edit the same day the text was deleted from here. (He failed to note this in the latter edit summary, although the former indicates it.) The text needs to be in the right place and deleted from the other(s). Sequential logic can point whereever it ends up. I didn't think it fit well in this article, but it doesn't seem to fit all that well in the history article either. Maybe it belongs in some third article. -R. S. Shaw (talk) 06:43, 13 February 2008 (UTC)
Yes I moved that content. This article is a brief introduction to this topic. I didn't see the sense of including a few areas of very esoteric research. These specific areas (optical and clockless) are very far from the mainstream. There are many other areas of research that are more popular - chip-multiprocessing, run-ahead fetching, etc. Dyl (talk) 06:45, 14 February 2008 (UTC)
Thank you, Dyl. That makes sense. So I'll re-move that content from this article to History of general purpose CPUs. --68.0.124.33 (talk) 05:46, 22 April 2008 (UTC)
Forgive me for moving that "asynchronous CPU" content yet again, to asynchronous circuit. --68.0.124.33 (talk) 01:27, 5 May 2008 (UTC)

[edit] needs refs

I found this a very interesting article to read, but it lacks refs. I've placed one fact tag in the economics section, but it really needs more. I'm hesitant to add the refimprove or related tags. Yngvarr 13:54, 31 August 2007 (UTC)

[edit] Proposed merger

The merger tag occured without anyone explaining why. Typical! A note and a reason should be put here, when placing a merger tag on the page, uglifying it. I think that a merger is unjustified. It's a common practice to have a short overview section in a main article and a longer detailed article on a more specific topic. I think the state as it is now, is pretty OK. However: the text in Central_processing_unit#Design_and_implementation could, if a mayhap editor get an arbitrary impulse to do so, be shrinked, and text moved to CPU design; or the other way around. It's not necessary to ask, or get a consensus over such a thing. Just do it! (Be bold!) Waiting for consensuses just takes a lot of time, sometimes to no avail. Use consensus as a tool mainly when conflicts arise. Said: Rursus ☻ 08:30, 9 June 2008 (UTC)

[edit] Too shallow on a too abstract level

I would like to have some "child-taleish" description like, the CPU has one or more registers, usually called A, B, C and similar. The CPU works by, one by one in sequence, pick an opcode from a list of opcodes, which is the program. The opcode is "interpreted" in a certain way, so that "F3" represents adding the value in B to A, setting the flags this-or-that if the number overflows, or "E8" "something" represents loading a value from memory at position numbered something.

The tale should go as following:

  1. CPU has registers/accumulators who are ... ,
  2. CPU reads a sequence of opcodes this that ... ,
  3. the PC (program counter) is a register that CPU keeps, in order to remember where in program code it picks opcode instructions ...,
  4. values can be added to or subtracted from PC, the instructions are called JUMP-this, JREL-that, in short "jumps", when such values are added, the CPU resumes execution at another place in the code,
  5. the SP (stack pointer) is another register that CPU uses to save and restore values,
  6. ... similar as for jumps but regarding CALLs/RETURNs involving saving position before calling ...

Then maybe a stop (?)

Related topic: Anybody who knows how many general CPU registers (SP, PC, cache and similar uncounted) that this or that CPU family has? It seems to me that the Intel family x86 has EAX, EBX, ECX and EDX summing to four. PowerPC? RSx000 (Nintendo?)? 68x00? Said: Rursus ☻ 08:47, 9 June 2008 (UTC)

I think that x86 has 8 general purpose registers, x64 has 16 and the RISC architectures (Alpha, MIPS, Power, SPARC and HP-PA) has 32 fixed point registers along with 32 floating point registers. Earlier revisions of SPARC and HP-PA may have less though, but I can't remeber how many. Rilak (talk) 08:58, 9 June 2008 (UTC)
Very good, thanks! I'll take a look outside WP to find relevant sources. Regarding my own proposal of content: its partially already written (on an abstract level) in Central processing unit#CPU operation, so the proposal can safely be ignored, until it reoccurs on Talk:Central processing unit. Cheers! Said: Rursus ☻ 10:01, 9 June 2008 (UTC)