Coding system of FireWire
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FireWire, also known as IEEE 1394, i.LINK (Sony) or DV (Panasonic), is a serial bus architecture for high-speed data transfer. Compared to older avionics data buses such as Mil-Std-1553, FireWire is a serial bus, meaning that information is transferred one bit at a time. Parallel buses utilize a number of different physical connections, and as such are usually much less efficient, more costly, and typically heavier [1]. Unlike other serial buses, such as PCI, FireWire fully supports both isochronous and asynchronous applications such as in safety-critical systems in the F-22 Raptor.
[edit] Encoding Scheme
FireWire uses Data strobe encoding (D/S encoding)[2]. In D/S encoding, two non-return-to-zero (NRZ) signals are used to transmit the data with high reliability. The NRZ signal sent is fed with the clock signal through an XOR gate, creating a strobe signal.[2]. This strobe is then put through another XOR gate along with the data signal to reconstruct the clock[2]. This in turn acts as the bus's PLL for synchronization purposes[2].
Data Strobe encoding is not the only feature of FireWire, however. FireWire is capable of operating safety critical systems due to the way multiple devices interact with the bus and how the bus allocates bandwidth to the devices. FireWire is capable of both asynchronous and isochronous transfer methods at once. Isochronous data transfers are transfers for devices that require continuous, guaranteed bandwidth[1]. Isochronous devices include control of the rudder, mouse operations and data from pressure sensors outside the aircraft. All these elements require constant, uninterrupted bandwidth. Asynchronous data transfers are for devices which use a buffer, such as streaming video, speakers and CD drives. To support both elements, FireWire dedicates a certain percentage to isochronous data and the rest to asynchronous data. In IEEE 1394 80% of the bus is reserved for isochronous cycles, leaving asynchronous data with a minimum of 20% of the bus[3].
The process of the bus deciding which node gets to transmit data at what time is known as arbitration[4]. Each arbitration round lasts about 125 micro-seconds[4]. During the round, the root node (device nearest the processor) sends a cycle start packet[4]. All nodes requiring data transfer respond, with the closest node winning[4]. After the node is finished, the remaining nodes take turns in order. This repeats until all the devices have used their portion of the 125 micro-seconds, with isochronous transfers having priority[4]. Up to 80% of the time can be given to isochronous nodes[4].
IEEE 1394a offers a couple of advantages over IEEE 1394. 1394a is capable of arbitration accelerations, allowing the bus to accelerate arbitration cycles to improve efficiency. It also allows for arbitrated short bus reset, in which a node can be added or dropped without causing a big drop in isochronous transmission[3].
IEEE 1394b on the other hand, uses a different encoding based on 8B/10B (Gigabit Ethernet & fiber channel). 8B/10B encoding involves expanding an 8 bit data word into 10 bits, with the extra bits after the 5th and 8th bit[5]. The partitioned data is sent through a Running Disparity calculator function[5]. The Running Disparity calculator attempts to keep the number of 1s transmitted equal to 0s[6]. Then, the different partitions are sent through a 5B/6B encoder for the 5 bit partition and a 3B/4B encoder for the 3 bit partition. In both cases, an extra bit is added to the nibble. This gives the packet the ability to have at least two 1s, enabling clock synchronization for reliable transfer[6].
