Talk:CAS latency

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I think this artical explains things quite well! As far as the math being "ridiculous", the way i see it is nothing more then someone trying to explain it in laymens terms as to how it works. (simplified for those of us who are not math wizards.) If you felt it is ridiculous, then I would be interested in seeing how you would lay it out in math terms. This is a subject that interests me as i am a network admin and deal with these problems on a daily basis. Knowing the formulas and how to figure all this out would help alot! Revision as of 13:32, 27 September 2006 by [1]

 Please help improve this article or section by expanding it.
Further information might be found on the talk page or at requests for expansion. (January 2007)

Contents

[edit] Integers?

AFAIK, CAS does not have to be an integer. For instance, a memory chip can have CAS latency 2.5. -thealsir

[edit] CAS2?

Could somone expand this page to include some info on CAS2 (CAS3, etc.?) Thanks! Ewlyahoocom 20:33, 10 April 2006 (UTC)

[edit] Errata

  • I have serious objections with the paragraph: <quote>"For example, consider a 133 MHz CL3 device (7.5 ns per cycle, 3 cycles request latency) versus a 100 MHz CL2 device (10.0 ns per cycle, 2 cycles request latency). The first bit would be available after 22.5 ns (7.5 ns * 3) on the CL3 device and after 20.0 ns (10.0 ns * 2) on the CL2 device, demonstrating the benefit of a lower CAS latency. However when reading a burst of even 4 bits, the higher clock speed wins: 45.0 ns (7.5 * 3 latency + 7.5 * 3 bits after the first) versus 50.0 ns (10.0 * 2 latency + 10.0 * 3 bits after the first)."</quote> The math is just plain wrong considering that DRAM is never accessible by individual bits. The smallest unit of download from or upload to DRAM is 1 byte (8 bits). Multiplying 7.5ns or 10.0ns for each bit is ridiculous. 208.48.228.132 00:04, 22 July 2006 (UTC)

[edit] About Bursts

The article clearly says "burst", that is several bits sequentially accessed on each bit lane, or several words of full bus width. Bus width is 8 or 16 bits, and there are (at least were) also 4 and 32 bit wide DRAM chips, but I can't remember if they were in the JEDEC spec. So a burst of 4 on an 8-bit wide device would read 32 bits.

[edit] Reply

The OP is taking the point of view from a single bit. In practice many bits (8/byte) are returned in parallel, but the timings are the same for each. 121.44.212.138 13:55, 3 April 2007 (UTC)

Actually - I think data is read in WORDS, not bytes, and not bits either - but anyhow - the author is referring to the fact that most memory access is sequential - reading lots and lots of *consecutive* bytes, meaning that the RAS stuff doesn't happen all that often.

203.206.137.129 12:16, 2 June 2007 (UTC)

Okay here's what I know about the issue at hand here. The Author is correct in the 7.5ns and 10ns example. Here's why: 1)Although bits are read and written in sets of 8 bits or 1 byte, the timings per bit would equal to those values because of the fact in common sense that it's ns and not ms or seconds here. 2)Sometimes even in certain RAM sticks that i've seen such as 8x 16 memory (I think that was the one anyways), it is read in sets of 16 bits or 2 bytes. If i'm wrong somebody correct me please. Vedalken 02:26, 23 June 2007 (UTC)

[edit] Are there compatibility Issues?

I just bought myself a wrong Ram 3.0 instead of the allready installed 2.5. Now I am wondering because the Motherboard manual suggests to have identical latencies.

In either way, there should be a statement about compatibility between different latencies. If there are compatibility issues this would be important. Though I haven't experienced any there might be a difference in speed.

LordManu 04:00, 3 January 2007 (UTC)

Dude

Get CPU-Z (free download) or any program that reads the "SPD table". That will tell you all the different frequency/latency settings that each module can use. The computer will run all of them at the same (highest unless your bios is set otherwise) frequency. e.g. If one module is 100, 133, 166 and another is 133, 166, 200; it will run at 166MHz.
If one has a CAS of 2.5 at 166Mhz and one has a CAS of 3 at 166MHz, it will run both of them at 3, but it will still work. The difference is practically unnoticable.--KX36 18:10, 29 May 2007 (UTC)

[edit] Analogy

I'm not an engineer but I if remember correctly from college, this analogy may help (pls correct errors).

Suppose you are a teacher taking a class on a field trip. A magic vehicle that will take your class is used by all the schools in the district. There is only a one way road that connects all the schools and the bus drives around from one school to the next all day waiting for students to pick up. When it get the order it will drive down the road passing the other schools until it get to yours. If it happens to be at your school when the call comes it can pick your students up right away but if it just left your school it will take time to drive all the way around to get back to your school. The complete circle is like the CAS.

You may ask, "Why not just stay at the first school and wait?" The answer is that if you are the last school it will always take the full time to get to you. By circling, the vehicle will usually be closer than that. In fact, it will be an average of half the distance to any school at any given time. (There are other technical reasons why it is done this way too.)

Other things to consider are the Memory Bus Speed and Memory Bus Width (size). The Memory Bus Speed is like the road speed limit and the Memory Bus Width is like the number of seats on the vehicle.

Now back to the trip. The vehicle arrives at your school. It has 10 seats and you have 50 students. 10 get in and are magically transported to their destination. The (now empty) vehicle has continued to move on to the next school. The rest of your class must wait for the vehicle to return.

Now, if the vehicle had more seats (Wider Memory Bus) or it could travel faster (Memory Bus Speed) or the route was shorter(CAS) your students could get to their destination quicker.

It is important to remember that the CAS is not really a distance on a road. It is the number of ticks on the system clock. The analogy is only useful to help you visualize why the CAS is not the only determining factor of memory speed. —The preceding unsigned comment was added by 157.130.64.90 (talk) 18:02, 6 April 2007 (UTC).

[edit] Timing Symbols

Should Trcd, Trp etc... be capitalised as tRCD, tRP, as per the SDRAM latency article? 82.195.186.33 13:10, 23 August 2007 (UTC)

[edit] Errata is wrong

The poster who posted the errata is simply wrong. The original poster is correct. For example, with DDR the chip is actually read 64 bits at a time, not 8 bits as some others have suggested.

When the original poster said the 1st bit would be available in 22.5 ns, he meant (and it's obvious) that the 1st 1 bit (deep) x 64 bits wide would be available. When he said 4 bits he meant that the 1st 4 bits (deep) x 64 bits wide would be available.

I have taken the liberty of adding some additional explanation to article and removing the misleading section tag. I am an infrequent editor and I do not know if removing the tag requires consensus or not, but if it does then I'm sure that someone can add it back.


—Preceding unsigned comment added by 72.147.48.164 (talk) 05:01, 11 September 2007 (UTC)

[edit] Timing units?

Thus CAS Latency (CL) is the time (in number of clock cycles) that elapses between the

In which clock cycles? CPUs or RAMs?--89.212.75.6 18:36, 2 November 2007 (UTC)


RAM ilovemrdoe 05:29, 30 December 2007 (UTC)

[edit] Sources?

There are no sources for most info. So its pure opinion. 82.43.183.13 (talk)

I wouldn't call it opinion, more 'general knowledge'. But some sources would be good! -ilovemrdoe 05:30, 30 December 2007 (UTC)

[edit] RAM speed increase versus CAS latency

According to the original article, i suppose that even though CAS5 is the minimum on DDR3 RAM, the clock speed boost will at some point offset the speed difference on even the smallest amount of data?

As in maybe DDR2-800 is faster at 4-4-4-12 but DDR3 may be faster in ALL situations at 5-5-5-15? Talrinys (talk) 11:58, 26 January 2008 (UTC)

[edit] Contradictions?

Am I being stupid, or does the simple advice "the lower the CAS the better" given directly contradict the table, in that the lower the CAS number in the table, the longer the total time is?