AMBA High-performance Bus
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AHB (Advanced High-performance Bus) is a bus protocol introduced in AMBA Specification version 2 published by ARM Ltd company. In addition to previous release, it has the following features:
- single edge clock protocol
- split transactions
- several bus masters
- burst transfers
- pipelined operations
- single-cycle bus master handover
- non-tristate implementation
- large bus-widths (64/128 bit)
A simple transaction on the AHB consists of an address phase and a subsequent data phase (without wait states: only two bus-cycles). Access to the target device is controlled through a MUX (non-tristate), thereby admitting bus-access to one bus-master at a time.
[edit] External links
- AHB To Wishbone project page - AHB to Wishbone bridge
- AMBA FAQ - from ARM
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